Scaling semiconductor devices by simply shrinking the device structure often does not produce acceptable results at small dimensions. For example, in NAND flash memory devices, when a floating gate is scaled the capacitive coupling (e.g., sidewall capacitance) of the floating gate is scaled accordingly with the surface area of the floating gate. As such, the smaller the surface area of the floating gate, the smaller the capacitive coupling between the floating gate and, for instance, a control gate. Typically, a trade-off that sacrifices capacitive coupling for scaling is acceptable provided the NAND memory device still functions. Unfortunately, the scaling is limited when the device node becomes sufficiently small such that the capacitive coupling between the floating gate and control gate becomes too small to effectively program the device at permissible operational voltages. Furthermore, parasitic capacitance (i.e., noise) between adjacent floating gates increases beyond the margin for read error of a system controller in a NAND memory device. Thus, a functioning NAND device is not possible under such conditions.
Further, the inventors have discovered that forming the floating gate to a smaller critical dimension and/or desired shape can result in undesired thickening of underlying layers, for example, such as a tunnel oxide layer in a NAND device using conventional oxidation processes.